Generally speaking, there are three distinct techniques of packaging a semiconductor device, in any case said package having leads or the like exiting the package for electrically connecting the packaged die to other components, either by mounting directly to a printed circuit board or by plugging the packaged device into a socket which in turn is mounted to a printed circuit board. These are: (1) plastic molding; (2) ceramic packaging; and (3) flat packing.
U.S. Pat. No. 5,051,813 (Schneider, et al.), incorporated by reference herein, provides an example of a plastic-packaged semiconductor device. Present plastic packaging techniques involve molding a plastic "body" around a semiconductor die. Prior to molding, the die is attached to a lead frame having a plurality of leads ultimately exiting the package for connecting the semiconductor device to external circuits, such as via conductors on a printed circuit board. Various forms of plastic packs are known, including DIP (Dual In-line. Package), PQFP (Plastic Quad Flat Pack) and PLCC (Plastic Leaded Chip Carrier). The lead frame is formed from a Single thin layer (foil) of conductive material, which is punched out to form individual leads. The inner ends of the leads are usually wire bonded to the active side (components, bond pads) of the die. When handling the lead frame, prior to the encapsulation, it is exceptionally important to avoid damaging the closely-spaced, delicate leads.
U.S. Pat. No. 4,972,253, incorporated by reference herein, provides an example of multi-layer ceramic packages which are laminated structures of alternate conducting and non-conducting layers, formed of thick conductive film and nonconductive ceramic, respectively. Generally, the conductive layers carry only one of signals, power or ground. This approach, particularly separating the signal plane (layer) from the ground and power planes, has distinct electrical advantages, which are well known. In this type of package, the conductive layers are screened or otherwise disposed between the nonconductive layers, and a very rigid, stable package is formed. For the signal-carrying layers, lead traces are typically screened onto an underlying ceramic layer. A die is eventually disposed into an opening in the package and connected to inner (exposed) ends of the lead traces. Generally, there is little problem in damaging the lead traces, since they are well supported by an underlying ceramic layer. Generally, vias are formed in the package to connect power and ground planes to particular leads in the signal plane.
U.S. Pat. No. 4,965,702, incorporated by reference herein, provides another example of a multi-layer package, using polymeric (e.g.) insulating layers and a copper foil (e.g.) for the conductive layers. Again, an object of such a multi-layer package is to provide for an electrical multilayer conductive package which partitions (separates) the power supply system of the package from the signal transmission system as much as practical in order to optimize the performance of both.
These two multi-layer ceramic and polymer packages are also known as "chip carriers" Both are preferably completely formed prior to mounting the semiconductor die within an opening in the chip carrier, and in both the inner leads are well-supported. Hence, both of these chip carriers inherently avoid the problem of lead damage during handling and mounting of the die.
FIGS. 1A and 1B show an example of tape-based flat packing. As illustrated herein, a semiconductor device assembly 10 includes an upper, segmented plastic film layer 14 (formed of segments 14A, 14B, 14C and 14D), a lower plastic film layer 16, metallic leads 18 sandwiched between the two plastic layers 14 and 16, a metallic (preferably copper) die attach pad 20 supported between the two plastic layers 14 and 16, a semiconductor device 22 mounted on the die attach pad 20 and bond leads 24 connecting the semiconductor device 22 to the leads 18. It is also known to employ conductive "bumps" on the inner ends of the leads, rather than bond wires, to connect the leads to the semiconductor die 22, in a tape automated bonding (TAB) process. The upper and lower plastic layers are suitably formed of polyimide, and form a thin, insulating supportive structure for the leads 18. A square, insulating ring ("body frame" or "dam") 26 is disposed atop the leads 18 between portions 14B and 14C of the upper plastic film layer, outside the die area. A layer-like quantity of silicone gel 28 is disposed over the die 22 and bond wires 24, and acts as an ionic contamination barrier for the die and as a stress relief for the leads 24 during assembly of the semiconductor device assembly, and further prevents an ultimate encapsulation epoxy 30 from contacting the semiconductor die. Evidently, the inner ends of the leads 18 are very fragile, and extreme care must be exercised when assembling the die 22 to the leads 18. In this respect, tape mounting a semiconductor die requires a similar degree of extreme care when mounting the die to the fine-pitch conductive leads.
Further examples of mounting semiconductor devices to a tape structure are shown in U.S. Pat. Nos. 4,800,419 and 4,771,330, incorporated by reference herein.
As used herein, the term "semiconductor device" refers to a silicon chip or die containing circuitry and bond sites on one face, and the term "semiconductor device assembly" refers to the semiconductor chip and associated packaging containing the chip, including external package leads or pins for connecting the semiconductor device assembly to a socket or a circuit board, and including internal connections (such as bond wires, TAB, or the like) of the chip to inner ends of the leads.
The aforementioned patents relate to semiconductor device assemblies having a high lead count, which is "de rigueur" in modern semiconductor devices. The plastic packaging and tape mounting techniques are generally indicative of methods of mounting semiconductor devices to preformed lead frames having a plurality of extremely delicate conductors connecting to the die. As mentioned above, there are generally two techniques for connecting a die to inner ends of lead frame conductors, namely wire bonding and tape-automated bonding (TAB). In TAB, "bumps," typically formed of gold, are located on either the die ("bumped die") or on the inner ends of the lead fingers ("bumped tape"). See, e.g., U.S. Pat. No. 4,842,662, FIGS. 5 and 6, respectively.
U.S. Pat. No. 4,842,662, incorporated by reference herein, discloses bonding integrated circuit components directly to a TAB tape, without the intermediary of a gold bump, by use of a process employing ultrasonic energy, pressure, time, heat and relative dimensions of the TAB tape. Generally, the end of a lead is "downset" (urged down) onto a die. (See column 6, lines 5-8). This may be thought of as a "bumpless" TAB process.
While the above-referenced patents teach various techniques of forming lead frames, TAB tapes, and the like, and various techniques for connecting semiconductor dies to same, these techniques generally involve only one layer, or plane, of patterned metal conductors (lead fingers), which single conductive layer represents a single plane carrying signals, power and ground to the semiconductor die.
As mentioned hereinabove, it is electrically desirable to provide distinct planes for carrying signal, power and ground from leads (or pins) exiting the package to the die within the package.
U.S. Pat. No. 4,933,741, incorporated by reference herein, discloses a multilayer package for integrated circuits having a ground plane (20) electrically isolated from a plane of conductors (14) by means of an insulating layer (16) formed of polyimide. The ground plane (20) is connected to selected conductors (14) by means of vias (18) extending through the insulating layer (16). The remaining (non-grounded conductors) carry signals and power to/from the integrated circuit device (11) As pointed out therein, "[b] because of the small physical size of the electrical conductors 14, they represent a significant impedance to operating potential and current 15 applied to the integrated circuit 11 causing an undesirable voltage drop along the length of the conductors 14. Additionally, capacitive coupling between the conductors 14 causes cross talk on the conductors 14 which apply signals to and/or derive signals from the integrated circuit 11. Further, the impedance of the conductors 14 create switching noise when the DC operating current 15 applied to the integrated circuit varies." And, as noted therein, "the capacitive cross coupling between the conductors 14 can be reduced by a [separate] ground plane 20 which also surrounds the integrated circuit 11 and is located adjacent the plurality of conductors." (See, especially, column 2, lines 31-46).
Despite the generally accepted notion that providing a separate ground plane has desirable electrical characteristics, the examples set forth above are limited to rigid, multi-layer ceramic or polyimide or polymer chip carriers. In both of these multi-layer approaches, it is relatively feasible to provide vias between separate metal layers and the intervening insulating layers.
On the other hand, in a tape-mounted, flexible substrate, semiconductor device assembly, it has generally not been very practical to consider or implement incorporating a distinct ground plane, since this type of "flexible" packaging does not lend itself readily to such a multi-layer approach employing vias spanning insulating layers.
For example, commonly-owned, co-pending U.S. patent application No. 07/829,977, entitled RIGID BACKPLANE FOR A SEMICONDUCTOR DEVICE ASSEMBLY, filed on Jan. 31, 1992, by Michael D. Rostoker, discloses an integrated circuit device package (semiconductor device assembly) having a flexible substrate including an upper patterned insularire layer, and a lower patterned conductive layer including a plurality of package leads (lead fingers). The assembly further includes a rigid or semi-rigid lower protective layer, formed of ceramic, glass, metal, plastic, and combinations thereof, which provides enhanced protection from mechanical and electrical degradation of the packaged device, and which may also serve as a heat sink. Thus we see that even though it is contemplated to have a rigid lower layer, which may be metal (i.e., electrically conductive), it is not contemplated to use the rigid lower layer as a ground plane connecting electrically to the die. (This is to be distinguished from the possibility that the rigid lower layer could be grounded to provide some shielding, but not connected within the package to the die.) The disclosure of this application is non-essential material.
The above described problems with conventional packaging techniques also affect packages incorporating a rigid leadframe in addition to or instead of etched conductive leads on a flexible support layer. Although the etched leads may be employed as an exit from the final package, and may provide a connection to external circuits and systems, in many applications a more rigid external lead is desirable. In such applications the leadframe may be bonded or otherwise attached to the existing etched leads. Alternatively, the etched traces may be eliminated altogether and the inner ends of the leadframe leads bonded to IC die bond sites using wirebonding or other suitable technique, the leadframe thus providing an interconnection between the die and external package pins.
A typical rigid leadframe usually includes a large number of leads, up to several hundred for complex ICs such as very large scale integrated (VLSI) Circuits. Selected leads typically carry reference potentials such as power and ground potential from external sources to the IC. Often one or more reference planes are used to convey these reference potentials. The leads of the leadframe selected to carry reference potentials are therefore electrically connected to these reference planes, sometimes at more than one location. The reference planes are typically continuous conductive layers surrounding the die and located in a plane parallel to the plane of the rigid leadframe. The reference planes serve to improve electrical performance by isolating power or ground signal paths from other signals and by providing a controlled impedance for the leadframe signal leads passing over the reference plane. Lead inductance and crosstalk between adjacent leads is thereby considerably reduced.
Under current practice selected leads of a rigid leadframe are typically connected to the reference plane at predetermined locations before the die is bonded into the package. One significant problem with this practice is that each leadframe is typically custom designed to provide a predetermined set of leads to reference plane interconnections appropriate for a particular application. Significant design effort and expense is therefore required to predetermine the interconnections between the leadframe and the reference plane that are suitable for a specific form of IC die. This effort usually must be repeated for every new IC die design. IC design and manufacturing costs are significantly increased as a result.
U.S. Pat. No. 5,032,895 discloses one available technique of providing interconnections between the leads of a leadframe and a reference plane. The packaging method therein involves a resin-encapsulated semiconductor quad flat package (QFP). An insulating film tape is formed with an IC mounting window and a number of bonding recesses or through holes. A metal plate is then bonded to the lower surface of the insulating film using an adhesive. A leadframe is then adhesively bonded to the upper surface of the insulating film. The leadframe includes both inner and outer leads. Both the inner and outer leads are supported by a tie bar temporarily attached to the outer leads of the leadframe. The IC die is then mounted to the metal plate within the mounting window defined by the insulating film. Wirebond connections are then provided between the bonding pads on the IC die and the inner leads of the leadframe. Certain selected inner and outer leads of the leadframe are also wirebonded to the metal plate through the bonding recesses in the insulating film. The resulting structure is then encapsulated with a resin mold to form a packaged IC. The metal plate thus serves as a reference plane and carries a voltage potential from some of the leadframe outer leads to the leadframe inner leads and thereby to the IC die.
In the above described exemplary prior art package and packaging method the interconnections between the leadframe and the metal plate reference plane are predetermined. Both the leadframe and the insulating layer are necessarily custom designed to accommodate these predetermined interconnect locations. Since the connections between the leadframe and the reference plane can only take place by wirebonding certain predesignated leadframe leads to the reference plane through predesignated bonding recesses, a leadframe design suitable for one IC will generally have to be redesigned to accommodate other ICs. This is a costly and inflexible approach to leadframe and reference plane interconnection during IC packaging.
Hence, we see that there are various desirable and unfulfilled objectives in the design and implementation of tape-mounted, flexible-substrate semiconductor device assemblies. There is also a need for more flexible approach to interconnecting select leads of a leadframe to a reference plane that is adaptable to many different IC die and package designs.